PCIe事務層及數據鏈路層的實現與驗證
發布時間：2018-07-16 15:09
【摘要】：總線遍布于整個計算機系統之中，使計算機系統的各個部分成為一個整體。它攜帶著有效信息，傳遞在計算機系統的不同部分之間，將各個部分的功能進行綜合來完成系統的功能。計算機速度不斷提高的今天，顯卡、內存、CPU等組成部分性能飛速發展，，總線日益成為計算機系統的性能瓶頸。 本課題來源于科研項目Fiber Channel協議芯片研制。由于目前行業內廣泛使用的PCI總線所能提供的最大帶寬為133MB/s，不能滿足該芯片的要求，因此本次芯片設計中采用第三代通用IO總線標準PCI Express協議。基于PCI Express協議的PCIe總線具有很多優良特性，如高帶寬，低延遲，抗干擾性強，高擴展性，高可靠性。PCIe總線采用點到點連接，保證了消息的實時性，基于交換器的設計，增加了下掛能力，使得PCIe的性能提升到一個新的層次。我們所要做的就是將PCIExpress協議的理論優勢轉化為實際應用中的優勢。 本次論文分為理論，實現及驗證三部分。理論部分根據PCI Express協議，介紹了PCI Express的基本概念，重點介紹了事務層和數據鏈路層的基本功能以及這兩層的數據包的構成方式和功能。實現部分基本按照PCI Express協議，以高性能，低延遲為目標，按照IC設計的流程，基本實現了PCI Express事務層和數據鏈路層的功能。事務層和數據鏈路層的設計各分為兩大模塊發送模塊和接收模塊，另外附加一些額外功能模塊，例如流量控制等。驗證的部分重點在于驗證平臺的搭建，本文中搭建的驗證平臺包含自動檢測模塊，對于驗證結果實現自動比對，大幅度減輕了驗證工作的效率。同時由于PCI Express設備即可作為根復合體，又可作為端點設備來工作，因此在本次驗證平臺的搭建中對協議代碼模塊進行的復用，降低了驗證平臺搭建的難度。最后對整個PCIe模塊進行了系統的驗證，并得到了較好的結果。
[Abstract]:The bus is spread throughout the computer system, making all parts of the computer system a whole. It carries the effective information and transmits between different parts of the computer system. The functions of each part are integrated to complete the function of the system. With the increasing of computer speed, the performance of graphics card and memory CPU is developing rapidly, and bus is becoming the bottleneck of computer system performance. This topic comes from the research project fiber channel protocol chip development. The PCI bus, which is widely used in the industry, can provide the maximum bandwidth of 133MB / s, which can not meet the requirements of the chip, so the third generation PCI Express protocol is adopted in the design of the chip. PCIe bus based on PCI Express protocol has many excellent characteristics, such as high bandwidth, low delay, strong anti-interference, high expansibility, high reliability. Increased the ability to hang down, so that the performance of PCIe to a new level. What we have to do is to convert the theoretical advantage of PCI Express protocol into the advantage of practical application. This paper is divided into three parts: theory, realization and verification. In the theoretical part, the basic concept of PCI Express is introduced according to PCI Express protocol, and the basic functions of transaction layer and data link layer are emphatically introduced, as well as the composition and function of these two layers of data packets. In the realization part, PCI Express transaction layer and data link layer are basically realized according to PCI Express protocol, high performance, low delay as the target, according to the flow chart designed by IC. The design of transaction layer and data link layer is divided into two modules: sending module and receiving module, and some additional function modules, such as flow control, etc. Part of the emphasis of verification is the construction of verification platform. The verification platform built in this paper contains automatic detection module. The verification results are compared automatically and the efficiency of verification work is greatly reduced. At the same time, the PCI Express device can be used as the root complex and the endpoint device to work, so the reuse of the protocol code module in this verification platform reduces the difficulty of building the verification platform. Finally, the whole PCIe module is systematically verified, and good results are obtained.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP336
本文編號：2126773
[Abstract]:The bus is spread throughout the computer system, making all parts of the computer system a whole. It carries the effective information and transmits between different parts of the computer system. The functions of each part are integrated to complete the function of the system. With the increasing of computer speed, the performance of graphics card and memory CPU is developing rapidly, and bus is becoming the bottleneck of computer system performance. This topic comes from the research project fiber channel protocol chip development. The PCI bus, which is widely used in the industry, can provide the maximum bandwidth of 133MB / s, which can not meet the requirements of the chip, so the third generation PCI Express protocol is adopted in the design of the chip. PCIe bus based on PCI Express protocol has many excellent characteristics, such as high bandwidth, low delay, strong anti-interference, high expansibility, high reliability. Increased the ability to hang down, so that the performance of PCIe to a new level. What we have to do is to convert the theoretical advantage of PCI Express protocol into the advantage of practical application. This paper is divided into three parts: theory, realization and verification. In the theoretical part, the basic concept of PCI Express is introduced according to PCI Express protocol, and the basic functions of transaction layer and data link layer are emphatically introduced, as well as the composition and function of these two layers of data packets. In the realization part, PCI Express transaction layer and data link layer are basically realized according to PCI Express protocol, high performance, low delay as the target, according to the flow chart designed by IC. The design of transaction layer and data link layer is divided into two modules: sending module and receiving module, and some additional function modules, such as flow control, etc. Part of the emphasis of verification is the construction of verification platform. The verification platform built in this paper contains automatic detection module. The verification results are compared automatically and the efficiency of verification work is greatly reduced. At the same time, the PCI Express device can be used as the root complex and the endpoint device to work, so the reuse of the protocol code module in this verification platform reduces the difficulty of building the verification platform. Finally, the whole PCIe module is systematically verified, and good results are obtained.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2013
【分類號】：TP336
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